Embedded DRAM applications demand both the utmost in high-performance CMOS (complementary metal oxide semiconductor) logic devices and high-density DRAM arrays. High-performance CMOS logic devices require low-resistance (on the order of 5 ohms/sq. or below) gate conductors and source/drain diffusions (salicidation), which drive processes that are costly and difficult to integrate with high-density DRAM processes. For example, salicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bitline contacts which are borderless to adjacent wordline conductors; also, salicided junctions in the array may result in increased current leakage of the memory device.
In a typical DRAM array, the wordlines need to be capped with an insulator, while in the supports the gate conductors must be exposed to allow the introduction of dual workfunction doping and salicidation. Conventional solutions to these integration problems require additional masking steps to remove the insulating gate cap from the support MOSFETs prior to the salicidation process.
Another problem encountered in prior art processes is the lithography steps used to simultaneously form support gates and wordlines: optimization of support gate lithography results in difficulties with defining wordlines in the array which are on a 2 F pitch.
Yet another problem with prior art processes is in the formation of local interconnects. Specifically, in the prior art one of the metallization levels, i.e., the M0 level, is used for both the bitline and for forming local interconnects. In the present invention, the conventional M0 metal is not required since the bitlines and local interconnects are formed by the salicidation of polysilicon.
In view of the drawbacks mentioned hereinabove with prior art processes of forming dual workfunction high-performance support MOSFETs in EDRAM arrays, there is a need for developing new and improved methods of manufacturing the same. That is, new and improved methods are needed for integrating high-performance CMOS logic devices with dense array MOSFET DRAM cells.